Introduction to Digital System Design
Update: 2003/01/27 Visitor：7528 Last Browsed：2009/11/19 02:29:06 PM

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Introduction

Course slides

Homework

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[2002/10/30] There will be 5 ~ 6 homeworks, 1 team project, and 2 exams.

[2002/10/30] The mid-term exam will take place in the last third part of November.

[2002/10/30] The professor will have a talk tomorrow morning, so there won't be any class in the morning. But there is still one class in the afternoon.
[2002/11/23] The mid-term exam will take place on the next thursday (11/28) at room 101

[2002/12/05] Project 2 Demo in Room 101.

[2002/12/18] The professor will participate in the ICS 2002 International Conference, so there won't be any class in this day.

[2002/12/30] The deadline of Project 3 is Jan. 9, 2003. The Final-Term Exam. is at Jan. 16, 2003.

[2002/12/30] The spec of Project 3 is in the "Homework" section.

[2003/01/27] The final grade is announced on the door of 421.

Teacher: 歐陽明 Prof. Ming Ouhyoung
TA: 劉秉周 Toby Liu toby@cmlab.csie.ntu.edu.tw
Office Hour:
Text Book: Contemporary Logic Design, by Randy H. Katz, 1994 ( 台北圖書 )
Content:
                1. Introduction to Boolean Algebra
                2. The Process of Design, Rapid Electronic System Prototyping
                3. Minimization of Boolean Function
                4. Combinational Circuits
                5. Programmable and Steering Logic (PLA, PAL, Gate Array, Multiplexers, etc)
                6. Sequential Logic Design
                7. Finite State Machine Design (VHDL, ABEL Languages, ASM Chart, etc)
                8. Case Study: ALU Design, Memory Conntrol
Evaluation: Homework 33%, Mid-term Exam 33%, Final-term Exam 34%

All course slides are scanned in images. Please click the following links to download them.

Slides 001 - 040 : Download
Slides 041 - 080 : Download
Slides 081 - 120 : Download
Slides 121 - 160 : Download
Slides 161 - 180 : Download

The final grade is announced on the door of 421.
2002/10/03 Homework #1: 1.6, 2.7, 2.13, 2.18, 2.19 ( no score yet )
2002/10/24 Homework #2: Program Demo ( decrease one degree for delayed one week )
Project 2: Download the Sample Program.
2002/12/30 Project 3 : Translate the state diagram into circuit layout. Requirement :
1. Support at least 32 states ( 5 flip-flops )
2. The input format can be VHDL or other Hardware description languages or defined by yourself.
3. Three basic problems : Textbook, 8.16, 8.13, 8.14 ; There will be another 3 problem announce at class.