What's New

The temporary score has been published, please contact with TA or me ASAP if you have any problem.

Syllabus

9/20	Introduction [PDF] [Print Version] Why and What is this course ? What is a computer ? Below your program Computer Hardware Digital Binary Systems READING: Chap. 1
9/27 10/4	Two-Level Combinational Logic [PDF] [Print Version] Logic Functions Gate Logic Two-Level Simplification READING: B.2, B.3 Homework #1 [PDF], deadline = 10/11
10/4 10/11 10/25	Instructions: Language of the Computer [PDF] [Print Version] Operations and Operands of the Computer Hardware Representing Instructions in the Computer Logical Operations Instructions for Making Decisions Supporting Procedures in Computer Hardware Communicating with People MIPS Addressing for 32-Bit Immediates and Addresses Translating and Starting a Program Arrays versus Pointers READING: Chap. 2 w/o 2.11~14, A.10 Homework #2 [PDF] [SPIM], deadline = 11/17~18
10/18	How to Program ? -- by TAs NOTE: the class of 10/18 will be started from 10:20.
11/1 11/8	Arithmetic for Computers [PDF] [Print Version] Signed and Unsigned Numbers Addition and Subtraction Constructing a Basic Arithmetic Logic Unit Multiplication and Division Floating Point READING: Chap. 3, B.5 Homework #3 [PDF], deadline = 11/22
11/15	HOLIDAY
11/22	Assessing and Understanding Performance [PDF] [Print Version] CPU Performance and Its Factors Measuring Performance READING: Chap. 4
11/29	mid-term exam. range: the materials until 11/22
12/6 12/13	The Processor: Datapath and Control [PDF] [Print Version] Memory Elements Building a Datapath A Simple Implementation Scheme Finite State Machines A Multicycle Scheme Exceptions Microprogramming READING: Chap. 5 w/o 5.8, B.7, B.8, B.10 Homework #4 [PDF], deadline = 12/20
12/20 12/27	Enhancing Performance with Pipelining [PDF] [Print Version] An Overview of Pipelining A Pipelined Datapath Pipelined Control Data Hazards and Forwarding Data Hazards and Stalls Branch Hazards READING: Chap. 6 w/o 6.7~9 Homework #5 [PDF], deadline = 1/3
1/3	Exploiting Memory Hierarchy [PDF] [Print Version] The Basic of Caches Measuring and Improving Cache Performance A Common Framework for Memory Hierarchies READING: Chap. 7 w/o 7.4 (virtual memory)
1/10	final exam. range: the materials until 1/3

Textbook

• David A. Patterson and John L. Hennessy. Computer Organization and Design: The Hardware/Software Interface, 3rd. ed. , Morgan Kaufmann, 2004.

Reference

• David A. Patterson and John L. Hennessy. Computer Architecture: A Quantitative Approach, ISE, 3rd ed. , Morgan Kaufmann, 2002.
  
• Randy H. Katz and G. Borriello. Contemporary Logic Design, 2nd ed. , Prentice Hall, 2004.

Grade Measurement

Homework (maybe five or six times with some small programs) + Examinations (twice) + Participants

Pre-courses

Logic Design (Introduction to Computer)